- The 24-Pin Receptacle Layout
- How Reversibility Works: The Configuration Channel (CC)
- SuperSpeed Differential Pairs: The High-Speed Signal Architecture
- USB 2.0 D+/D−: The Legacy Backbone
- SBU Pins: The Alt Mode Signal Highway
- VBUS and GND: Power Distribution Architecture
- Reduced Pin-Count Variants
- Signal Integrity Checklist for PCB Designers
- VITALCONN USB Type-C Connector Solutions
- Frequently Asked Questions
The USB Type-C connector looks deceptively simple — a small, symmetrical oval that works equally well plugged in either direction. But behind that reversible shell lies one of the most sophisticated signal architectures ever packed into a consumer connector: 24 pins carrying up to 80 Gbps of data, 240 W of power, and 8K video simultaneously, with a self-detecting orientation system that requires zero user input.
Understanding the USB Type-C pinout is essential for hardware engineers designing PCBs, procurement teams evaluating connector variants, and anyone who needs to debug USB-C signal integrity issues. This article breaks down the complete signal architecture — from the 24-pin layout to the Configuration Channel, differential pair routing, and Alt Mode signal mapping.
New here? This article focuses on the signal-level architecture. For a broader overview of USB-C connector types, power delivery, and selection criteria, see our companion guide: USB Type-C Connector: The Complete Guide.
The 24-Pin Receptacle Layout
The USB Type-C receptacle contains two rows of 12 pins — labeled Side A (A1–A12) and Side B (B12–B1) — arranged as mirror images. This rotational symmetry is what makes the connector reversible: regardless of how the plug is inserted, the same set of functional signals aligns with the host.
Complete Pinout Table (Receptacle Side)
|
Pin |
Side A |
Signal |
Direction |
Pin |
Side B |
Signal |
Direction |
|
1 |
A1 |
GND |
— |
12 |
B12 |
GND |
— |
|
2 |
A2 |
TX1+ |
Out |
11 |
B11 |
RX1+ |
In |
|
3 |
A3 |
TX1− |
Out |
10 |
B10 |
RX1− |
In |
|
4 |
A4 |
VBUS |
Power |
9 |
B9 |
VBUS |
Power |
|
5 |
A5 |
CC1 |
Bidir |
8 |
B8 |
SBU2 |
Aux |
|
6 |
A6 |
D+ |
Bidir |
7 |
B7 |
D− (B7) |
Bidir |
|
7 |
A7 |
D− (A7) |
Bidir |
6 |
B6 |
D+ (B6) |
Bidir |
|
8 |
A8 |
SBU1 |
Aux |
5 |
B5 |
CC2 |
Bidir |
|
9 |
A9 |
VBUS |
Power |
4 |
B4 |
VBUS |
Power |
|
10 |
A10 |
RX2− |
In |
3 |
B3 |
TX2− |
Out |
|
11 |
A11 |
RX2+ |
In |
2 |
B2 |
TX2+ |
Out |
|
12 |
A12 |
GND |
— |
1 |
B1 |
GND |
— |
Key insight: Side A’s TX1 maps to Side B’s RX1 (not TX1). This cross-mapping is deliberate — the plug’s TX pins connect to the receptacle’s RX pins on one side and vice versa on the other, enabling bidirectional data flow regardless of orientation.
Five Functional Signal Groups
|
Group |
Pins (Side A / Side B) |
Signal Purpose |
Impedance |
|
Power & Ground |
A1, A4, A9, A12 / B12, B9, B4, B1 |
4× VBUS + 4× GND; up to 48 V / 5 A (240 W) |
DC path |
|
SuperSpeed TX/RX |
A2–A3, A10–A11 / B2–B3, B10–B11 |
4 bidirectional differential lanes for USB 3.x / USB4 (up to 80 Gbps) |
90 Ω ±10% differential |
|
USB 2.0 |
A6–A7 / B6–B7 |
Legacy D+/D− (480 Mbps); duplicated for reversibility |
90 Ω ±10% differential |
|
Configuration Channel |
A5 (CC1) / B5 (CC2) |
Orientation detection, PD negotiation, VCONN |
Single-ended |
|
Sideband Use |
A8 (SBU1) / B8 (SBU2) |
Alt Mode auxiliary: DisplayPort AUX, audio, Thunderbolt sideband |
Application-dependent |
How Reversibility Works: The Configuration Channel (CC)
The CC pin is the most important signal in the Type-C architecture — it is the “brain” that makes reversibility possible without user intervention.
Orientation Detection Mechanism
When a plug is inserted into the receptacle, only one of the two CC pins (CC1 or CC2) connects to the cable’s internal CC wire. The other CC pin on the receptacle is left floating (open).
The detection process works as follows:
|
Step |
Action |
Signal Path |
|
1 |
Source (DFP) applies pull-up resistor Rp on both CC1 and CC2 |
CC1 ≈ CC2 ≈ voltage from Rp |
|
2 |
Sink (UFP) applies pull-down resistor Rd (5.1 kΩ) on its CC pin |
One CC line pulled low |
|
3 |
Source monitors both CC1 and CC2 voltages |
The CC pin that drops to ~0.41 V indicates connected orientation |
|
4 |
The other CC pin remains at Rp voltage → not connected |
Host now knows plug orientation |
|
5 |
Host activates SuperSpeed mux to route TX/RX to the correct lane pair |
TX1/RX1 or TX2/RX2 selected |
CC Pin Multi-Function: Beyond Orientation
The CC line is not just for orientation — it carries three additional critical functions:
|
Function |
How It Works |
|
Current advertisement |
Default current: Rp values encode 500 mA (USB 2.0 default), 1.5 A, or 3.0 A — all without PD protocol |
|
USB PD negotiation |
BMC (Biphase Mark Coding) modulation on the CC line transmits Power Data Objects (PDOs) for voltage/current negotiation up to 48 V/5 A |
|
VCONN supply |
The unconnected CC pin becomes VCONN — supplying power (typically 200 mW) to the cable’s E-Marker chip in electronically marked cables |
Design note: The CC line is a single-wire communication channel. All USB PD messaging — including 240 W EPR negotiation — occurs on this one pin pair, completely independent of the data pins. This is why a 16-pin (USB 2.0-only) Type-C connector can still support full 240 W charging.
SuperSpeed Differential Pairs: The High-Speed Signal Architecture
The SuperSpeed TX/RX differential pairs are where USB-C’s high-speed data magic happens. These four pairs (TX1±/RX1± on Side A, TX2±/RX2± on Side B) carry all USB 3.x and USB4 data.
Signal Pair Topology
|
Pair |
Side A Pin |
Side B Pin |
Function |
|
TX1+ / TX1− |
A2 / A3 |
— |
Host → Device transmit (Lane 1) |
|
RX1+ / RX1− |
— |
B11 / B10 |
Device → Host receive (Lane 1) |
|
TX2+ / TX2− |
— |
B2 / B3 |
Host → Device transmit (Lane 2, flipped orientation) |
|
RX2+ / RX2− |
A11 / A10 |
— |
Device → Host receive (Lane 2, flipped orientation) |
The SuperSpeed Mux Problem
Because the plug can be inserted in two orientations, the host cannot know in advance which TX/RX pair to use. The solution is a SuperSpeed multiplexer (mux) that switches between Lane 1 and Lane 2 based on the CC orientation detection:
Why not just short TX1 to TX2? At USB 2.0 speeds (480 Mbps), shorting D+ pins together is acceptable — the resulting stub is too short to matter. But at SuperSpeed rates (5–80 Gbps), a stub creates signal reflections that destroy signal integrity. The mux is mandatory for any design supporting USB 3.x or higher.
Impedance and Signal Integrity Rules
|
Parameter |
Requirement |
PCB Design Impact |
|
Differential impedance |
90 Ω ±10% (85–100 Ω acceptable) |
Requires controlled-dielectric stackup; stripline preferred for long routes |
|
Intra-pair skew |
≤ 5 mil (0.127 mm) length matching |
Serpentine traces to equalize D+ and D− lengths |
|
Inter-pair skew |
Minimize between TX and RX pairs |
Length match within ±50 mil for USB4 Gen 3/4 |
|
Via transitions |
Maximum 2 vias per pair |
Place mux close to connector; route on same layer if possible |
|
AC coupling capacitors |
220 nF on TX lines only (not RX) |
Place within 200 mils of the connector |
USB 2.0 D+/D−: The Legacy Backbone
The D+/D− pair carries USB 2.0 data at up to 480 Mbps. Unlike the SuperSpeed pairs, the D+/D− lines can be shorted together across both sides of the receptacle because the stub length is tolerable at 480 Mbps:
- A6 (D+) is shorted to B6 (D+) on the receptacle
- A7 (D−) is shorted to B7 (D−) on the receptacle
This means the USB 2.0 PHY always sees the same D+/D− pair regardless of plug orientation — no mux needed. This simplifies designs that only need USB 2.0 data.
D+/D− Specifications
|
Parameter |
Value |
|
Differential impedance |
90 Ω ±10% |
|
Data rate |
480 Mbps (High Speed), 12 Mbps (Full Speed), 1.5 Mbps (Low Speed) |
|
Capacitance |
≤ 200 nF (AC coupling optional, not required for USB 2.0) |
|
Length matching |
≤ 50 mil intra-pair skew |
SBU Pins: The Alt Mode Signal Highway
The Sideband Use (SBU1/SBU2) pins are the most flexible signals in the Type-C architecture. In normal USB operation, they are unused (floating). But when an Alternate Mode is activated, these pins carry protocol-specific auxiliary signals.
SBU Signal Mapping by Alt Mode
|
Alt Mode |
SBU1 (A8) |
SBU2 (B8) |
SuperSpeed Lanes Repurposed |
|
DisplayPort |
AUX+ (AUX CH positive) |
AUX− (AUX CH negative) |
2 or 4 lanes → DP Main Link |
|
Thunderbolt 3/4/5 |
Sideband (SB TX/RX) |
Sideband (SB TX/RX) |
All 4 lanes → TB bidirectional |
|
Audio Accessory |
MIC (microphone input) |
GND (analog ground) |
D+/D− → analog audio L/R |
|
VirtualLink |
DP AUX+ |
DP AUX− |
All 4 lanes → DP + USB 3.x |
Design note: SBU signals are low-speed (typically < 1 MHz for DisplayPort AUX), so they do not require strict impedance control or length matching. However, they should be routed away from high-speed SuperSpeed pairs to prevent crosstalk.
VBUS and GND: Power Distribution Architecture
The power pins are not a single VBUS and GND — they are four VBUS pins and four GND pins distributed across both sides. This multi-pin approach serves three purposes:
|
Design Reason |
Explanation |
|
Current sharing |
At 5 A (240 W), a single pin would overheat. Four parallel VBUS pins share the load, reducing per-pin current to 1.25 A. |
|
Redundancy |
If one contact degrades, the remaining three still carry current — fail-safe design. |
|
Reversibility |
VBUS must be available regardless of plug orientation. With pins on both sides, power connects in both orientations. |
VBUS Voltage Levels
|
Mode |
Voltage |
Max Current |
Max Power |
Trigger |
|
Default |
5 V |
500 mA (USB 2.0) / 900 mA (USB 3.x) |
2.5–4.5 W |
Rp default value |
|
1.5 A |
5 V |
1.5 A |
7.5 W |
Rp 1.5 A code |
|
3.0 A |
5 V |
3.0 A |
15 W |
Rp 3.0 A code |
|
USB PD (SPR) |
5–20 V |
3–5 A |
100 W |
PD negotiation on CC |
|
USB PD (EPR) |
28–48 V |
5 A |
240 W |
PD 3.1 EPR negotiation |
Thermal tip: At 48 V/5 A, the VBUS contact resistance becomes critical. Even 30 mΩ per contact generates 0.75 W of heat per pin — multiplied by 4 pins = 3 W localized heating. High-power USB-C connectors (like VITALCONN’s EPR-rated line) use 30 μ″ minimum gold plating and high-conductivity copper alloy to minimize contact resistance below 20 mΩ.
Reduced Pin-Count Variants
Not every application needs all 24 pins. The Type-C specification defines reduced variants that omit signal groups:
|
Pin Count |
Pins Present |
Removed |
Supports |
|
24-Pin (Full) |
All 24 pins |
— |
USB4 80 Gbps + 240 W PD + DP Alt Mode + Thunderbolt |
|
16-Pin |
VBUS, GND, D+/D−, CC1/CC2, SBU1/SBU2 |
8 SuperSpeed TX/RX pins |
USB 2.0 (480 Mbps) + 240 W PD — no video, no USB 3.x |
|
12-Pin |
VBUS, GND, D+/D−, CC1/CC2 |
8 SuperSpeed + 2 SBU pins |
USB 2.0 + PD up to 100 W |
|
6-Pin (Power-only) |
VBUS, GND, CC1/CC2 |
D+/D− + SuperSpeed + SBU |
PD charging only — no data |
Signal Architecture by Pin Count
|
Signal Group |
24-Pin |
16-Pin |
12-Pin |
6-Pin |
|
VBUS / GND (power) |
✅ |
✅ |
✅ |
✅ |
|
CC1 / CC2 (orientation + PD) |
✅ |
✅ |
✅ |
✅ |
|
D+ / D− (USB 2.0) |
✅ |
✅ |
✅ |
❌ |
|
TX/RX SuperSpeed (USB 3.x/4) |
✅ |
❌ |
❌ |
❌ |
|
SBU1 / SBU2 (Alt Mode aux) |
✅ |
✅ |
❌ |
❌ |
Cost optimization: If your device only needs USB 2.0 data and basic charging, a 16-pin Type-C connector eliminates 8 high-speed signal pads, removes the need for a SuperSpeed mux, and simplifies PCB routing to 2 layers. This saves both BOM cost and PCB complexity — a common choice for IoT sensors, Bluetooth devices, and budget accessories.
Signal Integrity Checklist for PCB Designers
|
Rule |
Requirement |
Why It Matters |
|
1. Differential impedance |
90 Ω ±10% for all TX/RX and D+/D− pairs |
Mismatch causes signal reflections → eye closure → data errors |
|
2. Intra-pair length matching |
≤ 5 mil for SuperSpeed; ≤ 50 mil for USB 2.0 |
Skew converts differential signal to common-mode noise |
|
3. SuperSpeed mux placement |
Within 500 mils of the connector |
Minimizes stub length on inactive lane |
|
4. AC coupling caps |
220 nF on TX lines, placed ≤ 200 mil from connector |
Blocks DC; required by USB 3.x specification |
|
5. Return path |
Continuous ground plane beneath all high-speed pairs |
Discontinuities cause impedance bumps and EMI |
|
6. Via count |
≤ 2 vias per differential pair |
Each via adds ~10–30 fF parasitic capacitance |
|
7. CC line routing |
Short, direct trace to PD controller; 5.1 kΩ Rd resistor close to connector |
Long CC traces pick up noise, corrupting PD communication |
|
8. ESD protection |
Place TVS diodes on all signal lines, ≤ 100 mil from connector |
USB-C ports are user-accessible — ESD events are common |
|
9. VBUS decoupling |
10 μF + 0.1 μF capacitor pair, placed close to VBUS pins |
Handles PD voltage transitions and switching transients |
|
10. Crosstalk |
≥ 3× trace width spacing between adjacent differential pairs |
Prevents coupling between SuperSpeed lanes |
VITALCONN USB Type-C Connector Solutions
At VITALCONN Electronics Technology, we manufacture USB Type-C connectors engineered for signal integrity across the full range of applications:
|
Product Line |
Pin Count |
Key Signal Features |
|
24-Pin Full-Featured |
24P |
All TX/RX + SBU; USB4 80 Gbps certified layout; 30 μ″ gold on all contacts |
|
16-Pin USB 2.0 |
16P |
Cost-optimized; no SuperSpeed routing needed; supports 240 W PD via CC/VBUS |
|
High-Power EPR |
16P/24P |
48 V-rated insulation; 5 A contacts; EPR-certified for 240 W applications |
|
Waterproof (IP67/IP68) |
16P/24P |
Sealed housing; signal integrity maintained in wet environments |
|
Locking / Industrial |
24P |
Screw-lock flanges; vibration-resistant; −40 °C to +85 °C |
All VITALCONN USB-C connectors feature:
- 90 Ω ±5% differential impedance (tighter than the ±10% spec requirement)
- Stainless steel shell with 360° EMI shielding
- 10,000 minimum mating cycles
- ISO 9001 quality management; RoHS / REACH / UL certified
📩 Request samples or technical datasheets: Email: sales@vitalconn.com | Phone: +86 755 21616271 🌐 www.vitalconn.com
Frequently Asked Questions
Q1: Why does USB Type-C use two CC pins instead of one? Two CC pins (CC1 and CC2) are required for orientation detection. When the plug is inserted, only one CC pin connects to the cable’s CC wire — the other becomes VCONN (powering the E-Marker chip) or floats. By monitoring which CC pin drops voltage, the host instantly determines plug orientation and switches the SuperSpeed mux accordingly.
Q2: Can I route D+ and D− from both sides of the receptacle, or should I only use one side? The USB Type-C specification explicitly allows shorting D+ (A6 to B6) and D− (A7 to B7) together on the receptacle. This is the standard practice because it eliminates the need for a mux on the USB 2.0 lines. The resulting stub is tolerable at 480 Mbps. Only route one D+/D− pair from the receptacle to your USB 2.0 PHY.
Q3: What happens if I use a 16-pin USB-C connector but my device needs DisplayPort output? It will not work. DisplayPort Alt Mode requires the SuperSpeed TX/RX lanes (which are removed in the 16-pin variant) to carry the DP Main Link, plus the SBU pins for the AUX channel. A 16-pin connector only supports USB 2.0 data and power delivery — no video output of any kind. If video is a current or future requirement, specify a 24-pin connector from the start.
Q4: Do the SBU pins need impedance-controlled routing? No. SBU signals are low-speed (DisplayPort AUX runs at ~1 Mbps). They do not require 90 Ω differential impedance or tight length matching. However, keep SBU traces at least 3× trace width away from SuperSpeed pairs to prevent crosstalk coupling.
Q5: What is VCONN and when is it needed? VCONN is power supplied to the cable’s electronics via the unused CC pin. It is required for electronically marked (E-Marker) cables rated above 3 A or supporting USB4/Thunderbolt. The E-Marker chip inside the cable communicates its current rating and data capabilities to the host via the CC line. Without VCONN, E-Marker cables cannot function, and the host will limit current to 3 A (max 60 W at 20 V).
VITALCONN Electronics Technology (Shenzhen) Co., Limited — Connecting the World with Precision ISO 9001 | ISO 14001 | RoHS | REACH | UL | 15+ Years of Manufacturing Excellence